标题:Flexible runtime verification based on logical clock constraints
作者:Yue D.[1,3]; Joloboff V.[1,3]; Mallet F.[1,2]
作者全称:Yue, Daian [1,3];Joloboff, Vania [1,3];Mallet, Frederic [1,2]
出版年:2017
关键词:clock constraint specification language; debugging; model driven engineering; property specification; Runtime verification; simulation; trace analysis; virtual prototyping
摘要:We present in this paper a method and tool for the verification of causal and temporal properties of embedded systems, by analyzing the trace streams 更多
收录类别:SCOPUS;EI
资源类型:外文期刊论文;外文会议论文
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